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'Crippling' IP Application Overheads Cause Telco Network Bottlenecks
Adax introduces SDCIII protocol accelerator to improve IMS performance and security
Telecommunications signaling vendor, Adax, is launching the SDCIII AMC, a protocol acceleration board designed to enhance IP network performance by offering both packet processing, IP security and signaling capabilities.
The SDCIII is able to reduce the processing burden placed on the network by offering computationally intensive functions such as SCTP packet processing, IPsec and SIP parsing. This capability relieves the CPU of some of the largest application overheads and makes the SDCIII ideal for deployment in IMS and Next Gen 3GPP wireless IP networks.
"IP signaling applications can help to lower operational expenditure, but they are already having a major impact on SCTP and SIP performance," explains Robin Kent, Director of Operations at Adax Europe. "System architects need to iron out potential bottlenecks now in anticipation of greater IP traffic volumes because a failure to do so will result in availability issues further down the line."
Its dedicated hardware enables the SDCIII to perform core functions to reduce impact on the CPU. This includes the checksum of inbound and outbound SCTP PDUs, which can account for up to 30 percent of the protocol overhead. The SDCIII facilitates IPsec through an integrated security engine, designed to offload the security functions key to IMS, such as key generation and exchange, authentication and bulk encryption.
"The inclusion of the security engine on the SDCIII is in response to the growing importance of IMS," explains Kent. "Whilst responsibility for security in the home network lies with the individual operator, the control point between the IMS 'home network' and 'visited network' must use IPsec in the Security Gateway. As more operators adopt IMS, it's inevitable that they will look for solutions like the SDCIII to run IPsec without compromising overall performance."
Other key features
* The SDCIII offers support for security protocols such as IPsec and DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms. It is also optimised to compute all of the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP and 802.11i.
* The SDC board features embedded Linux on its resident processor and supports IPsec/SCTP, which makes it an ideal solution for the following applications:
- Carrying the Diameter base protocol to support IMS interfaces, including Cx, Dx, Gmb, Rf, Ro, Sh, Si and Gi
- A SIP engine supporting the IMS SIP interfaces including Gm, ISC, Mg, Mi, Mm and Mw - A SIP Proxy / Security Gateway to support the SIP interface for VOIP
* The SDCIII will initially be available in AMC format and contains two dynamically configurable Gigabit Ethernet ports for high-volume IP applications. The board can also support the entire SIGTRAN stack in high volume environments.
General availability of the SDCIII AMC is scheduled for Quarter 2 2007. 13.02.2007, Adax
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